Digital System Design with VHDL & Verilog

Uplatz provides this comprehensive course on Digital System Design with VHDL & Verilog. This is a self-paced course consisting of recorded video lectures. You will be awarded Course Completion Certificate at the end of the course.

What is VHDL?

VHDL stands for Very High-Speed Integration Circuit HDL (Hardware Description Language). It is an IEEE (Institute of Electrical and Electronics Engineers) standard hardware description language that is used to describe and simulate the behavior of complex digital circuits.

VHDL is one of the two languages used by education and business to design FPGAs and ASICs. VHDL and Verilog are the two languages digital designers use to describe their circuits, and they are different by design than your traditional software languages such as C and Java.

The most popular examples of VHDL are Odd Parity Generator, Pulse Generator, Priority Encoder, Behavioral Model for 16 words, 8bit RAM, etc.

VHDL supports the following features:

• Design methodologies and their features.
• Sequential and concurrent activities.
• Design exchange
• Standardization
• Documentation
• Readability
• Large-scale design
• A wide range of descriptive capability

What is Verilog?

Verilog is also a HDL (Hardware Description Languages) for describing electronic circuits and systems. It is used in both hardware simulation and synthesis.

The most popular examples of Verilog are network switch, a microprocessor, a memory, a simple flip-flop, etc.

Difference between VHDL and Verilog

VHDL

1. It allows the user to define data types.
2. It supports the Multi-Dimensional array.
3. It allows concurrent procedure calls.
4. A mod operator is present.
5. Unary reduction operator is not present.
6. It is more difficult to learn.

Verilog

1. It does not allow the user to define data types.
2. It does not support the Multi-Dimensional array.
3. It does not allow concurrent calls.
4. A mod operator is not present.
5. Unary reduction operator is present.
6. It is easy to learn.

Why VHDL?

VHDL is used for the following purposes:

• For Describing hardware
• As a modeling language
• For a simulation of hardware
• For early performance estimation of system architecture
• For the synthesis of hardware

Advantages of VHDL

• It supports various design methodologies like Top-down approach and Bottom-up approach.
• It provides a flexible design language.
• It allows better design management.
• It allows detailed implementations.
• It supports a multi-level abstraction.
• It provides tight coupling to lower levels of design.
• It supports all CAD tools.
• It strongly supports code reusability and code sharing.

Disadvantages of VHDL

• It requires specific knowledge of the structure and syntax of the language.
• It is more difficult to visualize and troubleshoot a design.
• Some VHDL programs cannot be synthesized.
• VHDL is more difficult to learn.

Certificate of completion

Digital certificate - Included

Reed courses certificate of completion

Digital certificate - Included

• Digital System Design with VHDL & Verilog - all lectures 8:32:17

  • 1: Design for Testability 30:57
  • 2: Fault Simulation 27:45
  • 3: Test Vector Generation and IDDQ 15:07
  • 4: Timing Verification 19:10
  • 5: Boundary Scan 30:01
  • 6: VHDL - part 1 35:56
  • 7: VHDL - part 2 26:10
  • 8: VHDL - part 3 28:30
  • 9: Sequential Design 19:04
  • 10: State Machines 21:58
  • 11: State Reduction & Assignment 13:26
  • 12: State Machine Design & Analysis 20:56
  • 13: RTL Systems & RTL Design 31:50
  • 14: Verilog - part 1 37:16
  • 15: Verilog - part 2 31:03
  • 16: Verilog - part 3 30:55
  • 17: SystemVerilog - part 1 31:35
  • 18: SystemVerilog - part 2 26:17
  • 19: SystemVerilog - part 3 23:13
  • 20: Test Benches 11:08

Digital System Design with VHDL & Verilog - Course Curriculum

1. Design for Testability
2. Fault Simulation
3. Test Vector Generation and IDDQ
4. Timing Verification
5. Boundary Scan
6. VHDL
7. Sequential Design
8. State Machines
9. State Reduction & Assignment
10. State Machine Design & Analysis
11. RTL Systems & RTL Design
12. Verilog
13. System Verilog
14. Test Benches

This Digital System Design with Verilog and VHDL course covers the primary System Verilog advancements to the Verilog hardware description language (HDL), analyses the advantages of the new capabilities, and shows how employing System Verilog techniques may make design and verification more efficient and effective. The course is divided into two sections: The Design module looks at RTL design and synthesis improvements, while the Verification module looks at verification advancements such object-oriented design, assertions, and randomization.

The goal of this course is to help you gain knowledge about Field Programmable Gate Arrays (FPGAs) in order to create prototypes or products for a number of applications. Although FPGA design is a complicated topic, we will explain it in such a way that the basic ideas may be readily mastered with a little effort, while simultaneously offering a challenge for the more experienced designer. Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD) will be examined for their complexity, capabilities, and trends (CPLD). The abilities of conception, design, implementation, and debugging will be honed. Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD) will be examined for their complexity, capabilities, and trends (CPLD).

The abilities of conception, design, implementation, and debugging will be honed. We'll learn about embedded IP and processor cores, as well as the advantages and disadvantages of implementing vs purchasing IP. The newest software and FPGA development tools, as well as hardware platforms, will be used in the projects to assist establish a wide understanding of the capabilities of different Programmable SoC solutions.

Everyone

Passion and determination to achieve your goals!

• ASIC Design Engineer
• Electronics/Embedded Engineer
• Digital Design Engineer - RTL, ASIC, VHDL, Verilog, SystemVerilog
• RTL Design Engineer
• VHDL & Verilog - Designer Programmer
• Senior Design Verification Engineer
• Digital Design Verification / Test Engineer
• FPGA/ASIC Design Engineer
• Firmware Engineer - VHDL FPGA
• FPGA Hardware Design Engineer
• FPGA Verification Engineer
• Physical Design Engineer