Software Validation Engineer HW

JOB AD:

As a Senior EDA Software Validation Engineer, you will have opportunity to be part of a validation team with leading-edge Electronic Design Automation expertise and you will work on the most advanced SoC assembly and Hardware/Software interface flows.

You will join a proven-successful company, and be able to influence development environment, architecture, verification, and everything in-between.

Responsibilities:

Definition, documentation, development, and execution of validation tests for Register Bank compiler in Python, Perl and C++ language, able to run on any available RTL simulator (Cadence, Synopsys, etc.) and proficient with IP-XACT, UVM RAL and C HAL.

Maintain and enhance tests in the continuous integration flow, improve metrics, and increase automation.

Help improve and refine processes, methodologies, and metrics.

Experience, Requirements and Qualifications:

7+ years of industry experience as semiconductor CAD flow developer (Electronic Design Automation).

Demonstrated experience designing and building software frameworks to assemble and verify complex System-on-Chips.

Understanding of Hardware RTL design and verification languages (VHDL, Verilog, SystemC, C++, Python, Tcl, SystemVerilog) Knowledge of XML IP-XACT standard is a plus.

Experience with C / C++, Perl, Tcl and Python. Knowledge of Java is a plus.

Good written and verbal communication skills in both French and English Curious, autonomous, rigorous, and delivery-oriented with a commitment to quality and a thorough approach to the work.