Senior Verification Engineer

About the company:

• We are hiring a Senior Verification Engineer to work on advanced mixed-signal and MEMS-based ICs powering next-gen consumer, industrial, and automotive applications.
• Join a global leader with billions of units shipped and help shape the future of precision timing.

Key Responsibilities

• Develop SV-RNM models for analog and mixed-signal circuits .
• Create and execute verification plans based on chip/block specifications .
• Build UVM-based environments (scoreboards, monitors, sequencers, etc.) .
• Perform digital-top verification using SystemVerilog .
• Write SystemVerilog Assertions (SVA) and covergroups .
• Run simulations and debug results .
• Lead verification reviews for tape-out sign-off .
• Collaborate with cross-functional teams including analog, digital, test, and verification

Minimum Requirements:

• BS/MS in Electrical or Computer Engineering (MS preferred) . 5+ years (MS) or 8+ years (BS) of verification experience in semiconductors .
• Strong command of SystemVerilog, UVM, and scripting (Perl/Python) .
• Expertise in writing Assertions (SVA), covergroups, and simulation debug .
• Familiarity with Cadence Virtuoso and analog schematics .
• Understanding of digital design fundamentals (Verilog) .
• Comfortable working independently and across global engineering teams

Required experience:

• AMS verification experience with SV-RNM, Wreal, or V-AMS .
• Familiarity with UVM-AMS methodology and Formal Property Verification (FPV) .
• Background in analog/digital datapath designs (e.g., filters) .
• Object-oriented programming (e.g., C++) . Excellent communication and collaboration