IP Verification Engineer

Posted 29 April by Red King Resourcing
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IP Verification Engineer

Verification SV/UVM for TC48x NVM

Key Responsibilities:

  • Develop testbenches for a non-volatile memory IP
  • Creation of agents
  • Make adaptations to existing and create new tests for new features of the NVM IP
  • Show that the relevant tests are passing .
  • Define verification coverage .
  • Testbench Qualification using Certitude .
  • Documentation of verification results
  • Proof that relevant tests are passing .
  • Proof that verification coverage (structural and functional) is reached .
  • Proof that the testbenches have the required quality .

TSMC relevant-yes

Proven experience (5 years plus) in Digital IP verification using System Verilog / UVM

If you are interested in this role and would like to understand more then please click apply.

Reference: 52550965

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