DFT Engineer

Farnborough

Up to £120,000
Your new company

This exciting, multi-award winning global communications company is looking to expand its UK team to manufacture and support satellite tracking and IoT products and services. Established over ten years ago by leading voices in the satellite industry, they are seeking a knowledgeable and creative person with vision to join a team that develops truly global products.

Their products radically increase system performance and reduce the weight and power requirements of terminals, payloads and gateway equipment. With satellite communication expertise and full development capabilities, the company delivers the industry's smallest VSATs and multibeam electronically steered antenna arrays for a variety of mobile applications and services, such as Connected Car, IoT, consumer broadband, airline broadband communications, communication payloads and more.
We are looking for the best of the best, so if you are looking for a challenging new role in a dynamic company, read on!

Your new role

Join a dynamic and enthusiastic international Physical Design team, contributing to the development of cutting-edge Satellite SoCs throughout their entire life cycle: from design to production. These chips incorporate intricate digital and analogue modules and play a crucial role in the next-generation radiation-hardened satellite modems. As a team member, you'll have the opportunity to utilise top-tier EDA design tools while working with state-of-the-art process technologies.

Key Responsibilities:
DFT Integration for Complex SoCs and VLSI Devices: You will perform DFT insertion for intricate System-on-Chip (SoC) designs, VLSI devices, and test chips. This involves integrating custom designs and third-party IP components (such as hard IP, soft IP, I/Os, CPUs, and DSPs).

Comprehensive DFT Flow: Their DFT flow encompasses various stages, including Memory Built-In Self-Test (MBIST), scan insertion, and Automatic Test Pattern Generation (ATPG).

Collaboration with Logic Design RTL Team: You will collaborate closely with the Logic Design RTL team to establish timing constraints for implementation at both the block and chip top levels.

Integration of DFT Test Structures: As a team, you will insert DFT test structures and handle chip-level integration, capturing and simulating the design.

Skills needed to succeed.

• Understanding of ground level engineering processes.
• Experience with Tessent would guarantee an interview.
• DFT Insertion Flow: MBIST Insertion: Proficiency in integrating Memory Built-In Self-Test (MBIST) structures into designs.
• Scan Chains (Compress/De-compress) Insertion: Ability to set up scan chains for efficient testing.
• Hierarchical/Flatten Flow: Experience managing hierarchical and flatten design representations.
• ATPG Generation: Skill in generating Automatic Test Pattern Generation (ATPG) patterns.
• SDC (Synopsys Design Constraints) Support: Provide full SDC support for the physical team, ensuring seamless timing closure from synthesis to full-chip flatten Static Timing Analysis (STA).
• Pattern Generation:
• Proficiency in creating test patterns for functional validation.
• Tester ATE (Automatic Test Equipment) House Support:
• Problem-Solving and Analytical Skills:
• Scripting Languages Proficiency:
• Practical use of scripting languages such as Tcl, Python, and Perl to enhance workflows.
• Deep Knowledge of EDA Tool Flows:
• Effective Communication:
• The ability to collaborate with other design teams, 3rd party IP providers, library suppliers, and EDA tool vendors to improve scripts and optimise tool flow.
• Management and Interface with Sub-Contract Design Service Providers:

You don't need to tick all the boxes to apply, but a keen desire to improve your skills and learn on the job is needed!

If you're interested in this role, click 'apply now' to forward an up-to-date copy of your CV, or call us now.
If this job isn't quite right for you, but you are looking for a new position, please contact us for a confidential discussion about your career.

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