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Senior FPGA Design Engineer - VHDL - Ethernet - 6 Months

Posted 22 February by Premier Engineering Easy Apply Ended

Senior FPGA Design Engineer - VHDL - Ethernet - 6 Months

A client Dorset is looking for a Senior FPGA Design Engineer with Ethernet and Simulation experience. This will be for an initial 6 Month contract.


The client work on Marine systems, they need an experienced FPGA design Engineer to join their current team.

The candidate will need:

  • Synthesisable VHDL, Constraints, I/O Planning, Timing Closure, Floor Planning
  • VHDL Simulation and modelling (ActiveHDL, ModelSIM)
  • Implementation of Open Source Verification and Validation Methodologies (OSVVM)
  • Working with embedded software engineers
  • Embedded signal processing
  • Development processes and automated regression testing
  • Programmable logic design environments such as Xilinx Vivado & Altera
  • Scripting languages (TCL, Python)
  • Requirements capture (DOORS, Unified Modelling Language (UML))
  • SyncE / PTP (1588v2) protocols
  • 1G/10G Ethernet Media Access Controller (MAC)
  • IPv4 Internet protocol stack
  • Implementation of Ethernet OSI model in VHDL
  • Safety critical and high functional integrity based system design (DO-254/BS EN61508)

If you are interested in this role, please send your CV to Mark Jones at Premier Engineering

Premier are acting as an employment agency

Required skills

  • Senior FPGA Design Engineer - VHDL - Ethernet - 6 Months

Reference: 34531157

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