1. Thorough understanding of all commonly used Verilog/SystemVerilog constructs, fortified through detailed analysis of simulations using specially designed reference code.
2. Robust design techniques towards enhancing the reliability, performance, power, area and configurability that are key towards building a successful career in the VLSI design field.
3. Labs/mini-projects tailored towards developing a systematic design approach, guided by clear instructions combining screen-shots and expert tips.
4. Progressive design implementation exercises from simple examples to relatively more complex ones, each one coupled with simple SystemVerilog test-bench creation for design sanity checking.
5. Basic synthesis and gate-netlist schematic analysis exercises that help in building a hardware implementation perspective on top of the HDL coding skills
6. A design-automation example using Perl and exercises that provide a jump-start with Perl programming.
Upon successful completion of the course, the student will:
(1) Have in-depth knowledge and reference examples on SystemVerilog coding constructs.
(2) Achieve deeper understanding of key aspects related to:
? RTL coding considerations,
? Clock requirements
? Timing analysis
? Finite State Machines
? Power management
(3) Build sound awareness on the fundamentals of:
? Design for Test and Manufacturing (DFTM)
? Power-Performance-Area (PPA) trade-offs
? Bus Protocols and typical side-band signals
? Industry standard IP MMR interfaces based on AMBA APB and AXI4-Lite protocols.
(4) Obtain an overview of key aspects related to:
? Industry Standard IP and SOC design cycles
? Gate Netlist generation flows
? Physical design flows
(5) Understand how to systematically plan, partition, implement the RTL and create simple testbenches for simulating/debugging small-medium size IP designs.
(6) Gain confidence with basic IP design through implementation and touch-testing of a hierarchical IP with AMBA APB MMR programming interface and asynchronous clock domains.
(7) Gain sound familiarity with operating in a professional VLSI development environment that includes LINUX OS,usage of Perl programming for automation and ModelSim for simulations.
(8) Take away all the environment needed to conduct trial RTL implementation, simulations, synthesis and schematic analysis on his/her personal machine using the lab reference material and free EDA tool** installs.
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